The present invention relates to a demodulator for demodulating an input digital modulated wave, and, more particularly, relates to a digital signal demodulation circuit and a demodulation method of the digital signal processing type which are suitable for security of stable operation in a regeneration system under the condition of a low C/R or CNR (carrier-to-noise ratio) or in need of high-speed synchronization.
Heretofore, as systems for realizing a demodulator for demodulating an input digital modulated wave through digital signal processing, a system in which all circuits are synchronized with an operation sampling frequency has been mainly used as described in the paper entitled "Development of Small-Sized and Small-Capacity Earth Station Modulation/demodulation Portion LSIs", Lecture No. 2325, Collection of Papers in 1987 All Japan Meeting of the Institute of Electronics, Information and Communication Engineers of Japan.
Further, a system similar to that described above has been employed in a demodulator in a speech bandwidth wire modem, as described in the book entitled "Application of Digital Signal Processing", third edition, the Institute of Electronics and Communication Engineers of Japan, July 10, 1983, Chapter 6, Paragraph 6, Item 5, Page 169. In the aforementioned digital demodulators, the sampling frequency is synchronized with clocks extracted timely.
On the other hand, in a TDMA (time-division multi-access) system which is one of multiplex communication systems used in satellite communication etc., burst operation of a demodulator is required. In this instance, it is required to shorten the synchronizing time in carrier regeneration and in clock regeneration for the purpose of improving the efficiency of use of circuits. To this end, particularly in clock regeneration, there has been proposed a method in which a phase difference is absorbed in a short time after reception of a burst wave. For example, there has been proposed a system in which a preceding burst frequency difference is stored in a memory, as described in JP-A-60-183841.
All of the aforementioned conventional techniques belong to the category of a demodulation system in which processing is carried out in synchronism with a sampling frequency which is synchronized with a clock extracted timely.
FIGS. 2 and 3 show typical examples of the aforementioned prior art demodulators.
In FIG. 2 a reception modulated-wave signal 21 is sampled/quantized by an A/D converter 22 and then fed to a carrier synchronization portion 24 through a reception waveform shaping filter 23. The waveform shaping filter 23 and the carrier synchronization portion 24 operate in synchronism with a sampling period. A regenerated clock is obtained by a clock synchronization portion 26 which performs extraction/ synchronization of a clock component of data rate from a reception data 25 detected by the carrier synchronization portion 24. The regenerated clock is used to provide a sampling frequency 28 for determining the timing of operations of the various systems.
In FIG. 2, in the case where jitters of the regenerated clock increase under the condition of a low C/N, the quantity of the jitters corresponds to the sampling period so that the input noise into the carrier synchronization portion increases. Because the synchronization system operates coherently to the data rate, the characteristics of the feedback system change in accordance with the data rate. Accordingly, it is necessary to set invariables for optimizing the characteristics for every data rate.
On the other hand, a demodulation system for performing burst operation suited to a TDMA system is shown in FIG. 3. In FIG. 3, a reception modulated-wave signal 31 is sampled/quantized by an A/D converter 32 and then fed to a detector 33 and a carrier regeneration portion 34 so as to obtain a detected reception data 41. In order to make the operation of the timing extraction/synchronization on the basis of the reception data 41 be suited to the burst reception, information of a frequency difference is stored in an integral term within a loop filter 36. The output of the loop filter 36 which performs a perfect quadratic operation is accumulated in an accumulating memory 37 which in turn generates a control signal for controlling the frequency dividing operation of a variable frequency divider 38. The output of the variable frequency divider 38 is compared with the reception data 41 in a phase comparator 35 which in turn generates information as to a phase difference. Thus, a loop of a clock regeneration system is constituted.
In this circuit configuration, similarly to the previous example, the timing extraction clock is synchronized with the sampling frequency. In this system, in the case where little frequency difference exists in the inter-burst clocks, there occurs no phase jumping in the sampling clock in reception of a burst wave. However, differences in clock phase as well as in frequency between reception burst waves transmitted from terminal stations cannot be neglected throughout the whole system. Accordingly, clock initial phase jumping occurs in burst reception, even though this system is stored in memories as information with respect to every station. Consequently, the initial phase jumping exerts a bad influence such as a calculation error upon the carrier synchronization system. Furthermore, as a matter of course, regenerated clock jitters appear in the form of superimposition upon regenerated carrier jitters, so that carrier slip, asynchronism and the like occur more frequently under the condition of a low C/N.